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HD66113T
(120-Channel Common Driver Packaged in a Slim Tape Carrier Package)
Description
The HD66113T is a common driver for large dot matrix liquid crystal graphics displays. It features 120 channels which can be divided into two groups of 60 channels by selecting data input/output pins. The driver is powered by about 3V, making it suitable for the design of portable equipment which fully utilizes the low power dissipation of liquid crystal elements. The HD66113T, packaged in a slim tape carrier package (slim-TCP), makes it possible to reduce the size of the user area (wiring area).
Features
* * * * * * * * Duty cycle: About 1/100 to 1/480 120 LCD drive circuits High LCD driving voltage: 14V to 40V Output division function (2 x 60-channel outputs) Display off function Operating voltage: 2.5V to 5.5V Slim-TCP Low output impedance: 0.7 k (typ)
Ordering Information
Type No. HD66113TA0 HD66113TA1 Outer Lead Pitch (m) 190 240
Note: The details of TCP pattern are shown in The Information of TCP."
1
HD66113T
Pin Arrangement
X119 X120 Top view 140 121 V5L V2L DIO1 DISPOFF GND M DI CL DIO2 SHL CH V5R V6R VLCD2 V2R V1R VCC 119 120
Note: This figure does not specify the tape carrier package dimensions.
Pin Assignments
V1L VLCD1 V6L
140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
2
1 2
X1 X2
HD66113T
Pin Descriptions
Symbol VLCD1, 2 VCC GND V1L, V1R V2L, V2R V5L, V5R V6L, V6R CL M CH SHL DIO1 DIO2 DI DISPOFF X1-X120 Pin No. 140, 121 126 135 139, 122 136, 125 137, 124 138, 123 128 133 130 131 134 127 129 132 1-120 Pin Name VLCD VCC GND V1 V2 V5 V6 Clock M CH Shift left Data Data Data Display off X1-X120 Input/Output -- -- -- Input Input Input Input Input Input Input Input Input/output Input/output Input Input Output Classification Power supply Power supply Power supply Power supply Power supply Power supply Power supply Control signal Control signal Control signal Control signal Control signal Control signal Control signal Control signal LCD drive output
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HD66113T
Pin Functions
Power Supply VCC, GND: Supply power to the internal logic circuits. VLCD, GND: Supply power to the LCD drive circuits (Figure 1). V1L, V1R, V2L, V2R, V5L, V5R, V6L, V6R: Supply different power levels to drive the LCD. V1 and V2 are selected levels, and V5 and V6 are non-selected levels. Control Signals CL: Inputs data shift clock pulses for the shift register. At the falling edge of each CL pulse, the shift register shifts data input via the DIO pins. M: Changes the LCD drive outputs to AC. CH: Selects the data shift mode. (CH = high: 2 x 60-output mode, CH = low: 120-output mode) SHL: Selects the data shift direction for the shift register and the common signal scan direction (Figure 2). DIO1, DIO2: Input or output data. DIO1 is input and DIO2 is output when SHL is high. DIO1 is output and DIO2 is input when SHL is low. DI: Input data. DI is input to X61-X120 when CH and SHL are high, and to X60-X1 when SHL is low. DISPOFF: Controls LCD output level. A low DISPOFF sets the LCD drive outputs X1-X120 to the V2 level. A high DISPOFF is normally used. LCD Drive Outputs X1-X120: Each X outputs one of four voltage levels V1, V2, V5, or V6, depending on the combination of the M signal and the data level (Figure 3).
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HD66113T
VLCD1, 2 VCC GND
Figure 1 Power Supply for LCD Driver
SHL
Data shift direction
High
Shift to right DIO1 SR1 SR2 SR3 * * * SR120 DIO2
Low
Shift to left DIO2 SR120 SR119 * * * SR1 DIO1
Note: SR1 to SR120 correspond to the outputs of X1 to X120, respectively.
Figure 2 Selection of Data Shift Direction and Common Signal Scan Direction by SHL
M DATA X output level 1 V2 1 0 V6 1 V1 0 0 V5
Figure 3 Selection of LCD Drive Output Level
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HD66113T
Block Diagram
X1-X120 V1L, V2L, V5L, V6L VCC GND1, 2 VLCD1, 2 Shift register
Q SR1
******
LCD drive circuit
V1R, V2R, V5R, V6R M
Level shifter
Logic Shift register
DISPOFF CL
Q SR60 D
Q SR61 D
******
DIO1
Logic
D
Q SR 120 D
Logic
DIO2
SHL
CH
DI
6
HD66113T
Block Functions
LCD Drive Circuit The 120-bit LCD drive circuit generates four voltage levels V1, V2, V5, and V6, which drive the LCD panel. One of these four levels is output to the corresponding X pin, depending on the combination of the M signal and the data in the shift register. Level Shifter The level shifter changes logic control signals (2.5 V-5.5 V) into high-voltage signals for the LCD drive circuit. Shift Register The 120-bit shift register shifts the data input via the DIO pin by one bit at a time. The one bit of shiftedout data is output from the DIO pin to the next driver IC. Both actions occur simultaneously at the falling edge of each shift clock (CL) pulse. The SHL pin selects the data shift direction.
7
HD66113T
Absolute Maximum Ratings
Item Power supply voltage for logic circuits Power supply voltage for LCD drive circuits Input voltage 1 Input voltage 2 Input voltage 3 Operating temperature Storage temperature Notes: 1. 2. 3. 4. 5. Symbol VCC VLCD VT1 VT2 VT3 Topr Tstg Rating -0.3 to +7.0 -0.3 to +42 -0.3 to VCC + 0.3 -0.3 to VLCD + 0.3 -0.3 to +7.0 -30 to +75 -55 to +110 Unit V V V V V C C Notes 1, 5 1, 5 1, 2 1, 3 1, 4
The reference point is GND (0V). Applies to pins CL, M, SHL, DI, DISPOFF, and CH. Applies to pins V1 and V6. Applies to pins V2 and V5. Power should be applied to VCC-GND first, and then VLCD-GND. It should be disconnected in the reverse order. 6. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It should always be used within its specified operating range in order to prevent malfunctions or loss of reliability.
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HD66113T
Electrical Characteristics
DC Characteristics (VCC = 2.5V to 5.5V, GND = 0V, and T a = -30C to +75C, unless otherwise stated)
Item Input high voltage Symbol VIH Pins 1 1 2 2 3 1 4 -- -- Min 0.8 x V CC 0 VCC - 0.4 -- -- -5 -25 -- -- Typ -- -- -- -- 0.7 -- -- -- -- Max VCC 0.2 x V CC -- 0.4 1.0 5 25 0.5 1.0 Unit V V V V k A A mA mA I OH = -0.4 mA I OL = 0.4 mA I ON = 150 mA VIN = VCC to GND VIN = VLCD to GND f CL = 36 kHz f M = 75 kHz 2 1 Test Condition Notes
Input low voltage VIL Output high voltage Output low voltage Vi-Xj on resistance Input leakage current 1 Input leakage current 2 Current consumption 1 Current consumption 2 Note: Pins: 1. 2. 3. 4. VOH VOL RON I IL1 I IL2 I GND I LCD
CL, M, SHL, CH, DI, DIO1, DIO2, DISPOFF DIO1, DIO2 X1-X120, V V1, V2, V5, V6
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HD66113T
Notes: 1. Indicates the resistance between one of the pins X1-X120 and one of the voltage supply pins V1, V2, V5, or V6, when load current is applied to the X pin; defined under the following conditions: VLCD-GND = 40V V1, V6 = VCC - {1/20 (VLCD-GND)} V5, V2 = GND + {1/20 (VLCD-GND)} All voltages must be within V, VLCD V1 V6 VLCD - 7.0V, and 7.0V V5 V2 GND. Note that V depends on the power supply voltage VLCD-GND (Figure 5). 2. Input and output currents are excluded. When a CMOS input is left floating, excess current flows from the power supply through the input circuit. To avoid this, VIH and VIL must be held at VCC and GND, respectively.
VLCD V1 V V6
V
V5 V2 GND
Figure 4 Relation between Driver Output Waveform and Voltage Levels
6.4 V (V) 2.3
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14
40
VLCD-GND (V)
Figure 5 Relation between VLCD-GND and V
10
HD66113T
AC Characteristics (VCC = 2.5V to 5.5V, GND = 0V, and T a = -30C to +75C, unless otherwise stated)
Item Clock cycle time Clock high-level width Clock low-level width Clock rise time Clock fall time Data setup time Data hold time Data output delay time M phase difference Output delay time 1 Output delay time 2 Symbol t CYC t CWH t CWL tr tf t DS t DH t DD tM t pd1 t pd2 Pins CL CL CL CL CL DI, DIO1, DIO2, CL DI, DIO1, DIO2, CL DIO1, DIO2, CL M, CL X (n), CL X (n), M Min 400 30 370 -- -- 100 30 -- -300 -- -- Max -- -- -- 30 30 -- -- 350 300 1.2 1.2 Unit ns ns ns ns ns ns ns ns ns s s 3 3 2 1 1 Notes
AC Characteristics (VCC = 5.0 V 10%, GND = 0 V, and T a = -30C to +75C, unless otherwise stated)
Item Clock cycle time Clock high-level width Clock low-level width Clock rise time Clock fall time Data setup time Data hold time Data output delay time M phase difference Output delay time 1 Output delay time 2 Symbol t CYC t CWH t CWL tr tf t DS t DH t DD tM t pd1 t pd2 Pins CL CL CL CL CL DI, DIO1, DIO2, CL DI, DIO1, DIO2, CL DIO1, DIO2, CL M, CL X (n), CL X (n), M Min 400 30 370 -- -- 100 30 -- -300 -- -- Max -- -- -- 30 30 -- -- 150 300 0.7 0.7 Unit ns ns ns ns ns ns ns ns ns s s 3 3 2 1 1 Notes
Notes: 1. t r , t f < (tcyc - tCWH - t CWL)/2 and tr, t f 30 ns 2, 3 The load circuit shown in Figure 6 is connected.
11
HD66113T
Test point *2: 30 pF *3: 100 pF
Figure 6 Load Circuit
tf 0.8 x VCC 0.2 x VCC tDD DIO1, DIO2/ DI (input) tDS 0.8 x VCC 0.2 x VCC tDH tr
tCWL
tCWH
tCYC
CL
DIO1, DIO2 (output) tM M
0.8 x VCC 0.2 x VCC
0.8 x VCC 0.2 x VCC tpd2
X (n) tpd1
Figure 7 LCD Controller Interface Timing
12
1 frame 1 frame
M
DIO (input)
120 121 122 123 240 1 2 3 120 121 122 123 240 1 2 3
240 1
2
3
Operation Timing (1/240 Duty Cycle)
From LCD controller
CL
X1 (COM 1) V1 V5 V5 V1
V5
V2 V6
V2 V6 V6 V2
X2 (COM 2)
V5 V6 V2
HD66113 No. 1
X120 (COM 120) V2 V5
V5 V6
V1
V6
DIO (output)
X1 (COM 121) V2
V5 V6
V5
V1
V6 V5 V1
HD66113 No. 2
X2 (COM 122) V2
V5 V6
V6
X120 (COM 240)
V5 V1 V6
V2 V5
V1 V6
HD66113T
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HD66113T
Connection Examples
Figures 8 and 9 show examples of how HD66113Ts can be configured to drive a 600-line LCD panel with a 1/300 duty cycle. Figures 10 and 11 show examples of how HD66113Ts can be configured to drive a 240-line LCD panel with a 1/240 duty cycle. The HD66113T's 120 channels can be divided into two groups of 60 channels, and its data shift direction can be changed by selecting the data output mode pin (CH) and data shift pin (SHL), respectively.
LCD panel DATA DIO1 (Data of lines 1 to 300) IC1 (SHL = high, CH = low) DIO2 X120 DIO1 IC2 (SHL = high, CH = low) DIO2 X120 IC3 (SHL = high, CH = high) DIO1 X1 Line 240 Line 241 Line 300 Line 301 Line 360 Line 361 X1 Line 120 Line 121 X1 Line 1
X60 DATA DI X61 (Data of lines 301 to 600) DIO2 X120 DIO1 X1
IC4 (SHL = high, CH = low)
DIO2 X120 DIO1 IC5 (SHL = high, CH = low) DIO2 X120 X1
Line 480 Line 481
Line 600
Segment driver
Figure 8 Dual-Screen Configuration of a 600-Line LCD Panel with a 1/300 Duty Cycle (1)
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HD66113T
LCD panel DIO1 X1 Line 1
IC1 (SHL = low, CH = low) DIO2 X120 DIO1 IC2 (SHL = low, CH = low) DIO2 X120 DIO1 DATA (Data of lines DI 1 to 300) IC3 (SHL = low, CH = high) X1 X60 X61 Line 240 Line 241 Line 300 Line 301 Line 360 Line 361 X1 Line 120 Line 121
DIO2 X120 DIO1 X1
IC4 (SHL = low, CH = low)
DIO2 X120 DIO1 IC5 (SHL = low, CH = low) DATA DIO2 X120 (Data of lines 301 to 600) X1
Line 480 Line 481
Line 600 Segment driver
Figure 9 Dual-Screen Configuration of a 600-Line LCD Panel with a 1/300 Duty Cycle (2)
15
HD66113T
LCD panel DATA DIO1 (Data of lines 1 to 240) IC1 (SHL = high, CH = low) DIO2 X120 DIO1 IC2 (SHL = high, CH = low) X1 Line 120 Line 121 X1 Line 1
DIO2 X120
Line 240 Segment driver
Figure 10 Single-Screen Configuration of a 240-Line LCD Panel with a 1/240 Duty Cycle (1)
16
HD66113T
LCD panel DIO1 X1 Line 1
IC1 (SHL = low, CH = low) DIO2 X120 DIO1 IC2 (SHL = low, CH = low) X1 Line 120 Line 121
DATA DIO2 X120 (Data of lines 1 to 240)
Line 240 Segment driver
Figure 11 Single-Screen Configuration of a 240-Line LCD Panel with a 1/240 Duty Cycle (2)
17
HD66113T
Notes on Power-On/Off of the LCD Driver
To prevent an LCD driver display error at power on/off, the sequence for power-on signal activation must be as follows (see Figure 12):
2.7V VCC
2.7V
0ms VLCD
0ms
0ms
0ms
DISP
Input signals such as CL1, CL2, and Data
Signal non-fixed period
Initializing period (1frame or longer)
Figure 12 Sequence of Power-On/Off At Power On (1) Power on VCC. At this time, input 0 to the DISP pin. (2) Display-off function forces the LCD driver to output a V2 level (lowest level). (3) Display-off function takes priority even if the input signal status becomes irregular immediately after VCC power-on. (4) Input the specified signals to initialize registers of the LCD driver. Its period must be 1 frame or longer. (5) Set the DISP level to 1 to cancel display-off function after steps (1) to (4). At this time, VLCD and each V pin input must be at the specified levels.
18
HD66113T
At Power Off Basically, the power-off procedure is the reverse of the power-on procedure. (1) Set the DISP level to 0. (2) Lower LCD driver power supply to 0V (3) Lower VCC and each input signals to 0V At this time, each V pin input must be at 0V. Display-off function stops when V CC falls to 0V, and therefore, the LCD driver may output a level other than V2 (lowest level). As a result, a display error may be caused at power-off or power-on.
19
HD66113T
LCD Driver LSI Power Supply Pin Connection
A feature of the LCD driver is the LCD drive power supply. As the number of pixel drives per LSI increases, so does the voltage and number of outputs. Consequently, if multi-output CMOS circuits are switched simultaneously, a wiring voltage drop may occurs due to transient currents, and the potential between the LCD drive circuit power supply (VLCD) and LCD drive level power supplies (V1, V6, and V3) or GND and the LCD level power supplies (V2, V5, and V4) may be inverted, resulting in latchup breakdown. To prevent this, it is recommended that, when designing the LCD drive power supply and board power supply wiring, the power supply wiring be designed as low-impedance and capacitors be inserted in the wiring between VLCD and V1, V3, V6, and between V2, V4, V5 and GND. In set evaluation, it is recommended that a check be carried out to confirm that there is no inversion of the LCD drive power supply and level power supplies in the period between when the LCD drive power supply is turned on and turned off.
Example of capacitor insertion (when VLCD = V1 and GND = V2) VLCD, V1 pins (COM, SEG) V6 pin (COM)
+ -
+ -
+ -
+ -
Electrolytic capacitor
V3 pin (SEG)
V4 pin (SEG)
Ceramic capacitor
V5 pin (COM)
+ - + -
GND, V2 pins (COM, SEG)
Figure 13 Example of Capacitor Insertion
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